Talk

All through the analog age, for humans it has been easy to forget, and hard to remember. In the digital age, the situation has reversed: today the default is to store and remember; forgetting has become the exception. This has profound consequences for individuals and society, from how (informational) power is allocated to whether and how we retain our capacity to act in time. In this talk I analyze these consequences as well as possible solutions - legal and technical - to address the challenge posed by comprehensive digital memory.

Measurement is a powerful and indispensable technique for discovering the state of the network and for assisting operational management of networked systems to ensure good performance and security properties. Designing the effective measurement technique depending on the problem context is especially challenging for Internet-based systems due to issues such as a lack of access, overhead concerns, and measurement noise. In this talk, I present our experience in designing and deploying measurement systems for several important applications, e.g., diagnosing routing performance disruptions and prefix hijacking attacks from end systems, uncovering spammer behavior through campaign-based analysis, and detecting network neutrality violation in backbone ISPs. I will summarize lessons learned and discuss our future work on applying intelligent measurement to relatively new application domains such as data cellular networks and data center systems.

Bio:
Z. Morley Mao is an assistant professor of Computer Science and Engineering at the University of Michigan. Morley received most of her degrees (Ph.D., M.S., and B.S.) from the University of California at Berkeley. She is a recipient of the NSF CAREER award in 2007, an IBM Faculty Award in 2008, Sloan Research Fellowship in 2009, and was recently named the Morris Wellman Faculty Development Professor at Michigan. Her research interests encompass network measurements, routing protocols, distributed systems, and network security.

Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significant scaling challenges in the presence of ever-increasing routing table growth and churn. Recent advances in programmable hardware and high-level hardware description languages provide the opportunity to implement BGP directly at the hardware layer. Hardware-based implementation allows designs to take advantage of the parallelization and customizability of the underlying hardware to improve performance. As a first step in this direction, we design and implement a hardware-based BGP architecture. To understand the challenges in doing this, we propose an architecture and logical design for the core components of BGP running as a logical circuit in an FPGA. We then enumerate sources of complexity and performance bottlenecks, and derive modifications to BGP that reduce complexity of hardware offloading. Our results based on update traces from core Internet routers indicate an order of magnitude improvement in processing time and throughput.