Due by 5 PM, Monday Oct. 14, 1996
The first three problems ask you to explore adding the MIPS instruction jal to the multi-cycle implementation of Chapter 5; the next three ask the same for the addiu instruction. Then three more problems ask you to implement an instruction that might be in the MIPS architecture, but isn't. Be sure to use the corrected Figures from the handout!
1. (5 points) Exercise 5.3 from the text.
2. (5 points) Exercise 5.4 from the text.
3. (5 points) Exercise 5.5 from the text.
4. (5 points) Exercise 5.13 from the text.
5. (5 points) Exercise 5.14 from the text.
6. (5 points) Exercise 5.15 from the text.
Now that you're getting good at this, consider an instruction that is not in the MIPS architecture (but was in EDSAC, you'll recall): add memory to register. Let's call the instruction ``add memory'' with opcode addm and this meaning:
addm $rt,disp($rs) means $rt = $rt + Memory[$rs + disp]
That is, addm has exactly the same format as lw, but it adds the memory location to the register instead of merely loading it.
7. (5 points) Show the additions to the datapath and control lines of Figure 5.35 needed to implement addm in the multi-cycle datapath.
8. (5 points) Show the steps in executing the addm instruction in the multi-cycle datapath, using the style of the step breakdown used in pages 362-365, but using more steps if needed.
9. (5 points) Show the additions to the finite-state machine of Figure 5.43 needed to implement the addm instruction.
10. (5 points) Compare the addm instruction to the alternative lw and add in the context of the multi-cycle datapath. Consider performance (number of cycles for each), use of registers, and anything else you think important. Is either choice clearly superior?
11. (1 point) How long did this take you, not counting the reading, and with whom did you work?