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for class on Thursday Dec. 5, 1996
Please read section 5 of the MIPS R10000 Document Handout.
In this class we will address issues at the ``back'' end of the R10000 processor, including the cache and TLB structure. We will also consider how a compiler might relate to this design: how should dynamic execution, branch prediction, and the other fancy features of the chip influence the compiler's choice and arrangement of instructions?