This seminar will use a discussion format; all students will be expected to participate. Coursework will include reading, preparation of assigned discussion topics, presenting papers, some design exercises, and possibly a final paper or project.
While the seminar will be aimed at first- and second-year graduate students, interested undergraduates are welcome.
Monday: Introduction to the course
Wednesday: Latches, flip-flops, terminology, basic analysis (lecture)
Monday: Deeper analysis of simple clocked designs (lecture)
Wednesday: Unger and Tan, "Clocking Schemes for High-Speed Digital Systems," IEEE Trans. on Computers C-35, 10 (Oct. 1986), pp. 880-895.
Monday: Sakallah, Mudge, and Olukotun, "Analysis and Design of Latch-Controlled Synchronous Digital Circuits," IEEE Trans. on Comp.-Aided Design 11, 3 (March 1992), pp. 322-333.
Wednesday: Harris, Horowitz, and Liu, "Timing Analysis Including Clock Skew," IEEE Trans. on Comp.-Aided Design of Integrated Cicuits and Systems 18, 11 (Nov. 1999), pp. 1608-1618. pdf
Monday: Leiserson and Saxe, "Retiming Synchronous Circuitry," Algorithmica 6, 1 (1991), pp. 5-35.
Wednesday: Lockyear and Ebeling, "The Practical Application of Retiming to the Design of High-Performance Systems," Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1993, pp. 288-295. pdf
Monday: Hallin and Flynn, "Pipelining of Arithmetic Functions," IEEE Trans. on Computers C-21, 8 (Aug. 1972), pp. 880-886; also Smith, "An Analysis of Pipeline Clocking," Univ. of Wisconsin, March 1990. ps
Wednesday: Sakallah, Mudge, Burks, and Davidson, "Synchronization of Pipelines," IEEE Trans. on Comp.-Aided Design of Integrated Cicuits and Systems 12, 8 (Aug. 1993), pp. 1132-1146.
Friday: Design exercise due by 5 PM
Monday: Chaney and Molnar, "Anomalous Behavior of Synchronizer and Arbiter Circuits," IEEE Trans. on Computers C-22, 4 (April 1973), pp. 421-2; also Walker and Cantoni, "A New Synchronizer Design," IEEE Trans. on Computers 45, 11 (Nov. 1996), pp. 1308-1311.
Wednesday: No class
Monday: Dobberpuhl, et al., "A 200-MHz Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits 27, 11 (Nov. 1992), pp. 1555-1567.
Wednesday: Bailey and Benschneider, "Clocking Design and Analysis for a 600-MHz Alpha Microprocessor," IEEE Journal of Solid-State Circuits 33, 11 (Nov. 1998), pp. 1627-1633.
Monday: Review of pipeline-clocking design exercise
Wednesday: Pountain, "Computing Without Clocks," BYTE, Jan. 1993, pp.145-150; also Furber, "The Return of Asynchronous Logic," Tech.. Report, Univ. of Manchester, 1993, html
Monday: Sutherland, "Micropipelines," CACM 32, 6 (June 1989), pp. 720-738.
Wednesday: No class
Monday: Day and Woods, "Investigation into Micropipeline Latch Design Styles," IEEE Trans. on VLSI Systems 3, 2 (June 1995), pp. 264-272.
Wednesday: Martin, et al.,"The Design of an Asynchronous MIPS R3000 Microprocessor," Proc. 17th Conf. on Advanced Research in VLSI, Los Alamitos, CA, 1997. ps
Monday: Self-clocking schemes (lecture)
Wednesday: Burleson, Ciesielski, Klass, and Liu, "Wave-Pipelining: A Tutorial and Research Survey," IEEE Trans. on VLSI 6, 3 (Sept. 1998), pp. 464-474. pdf
Monday: Niemier and Kogge, "Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies," Proc. 28th ISCA, Göteborg, Sweden, July 2001, pp. 166-177. pdf
Wednesday: Course summary, feedback, and wrap-up